In recent years, more and more hardware accelerators are customized for deep learning (DL) computation to improve the throughput of inference and the performance per watt. In DL applications, convolutions are the major computation. The convolution can be regarded as a special matrix multiplication, which utilizes multiplier-accumulators for hardware implementation. In a multiplier-accumulator, the critical path and some paths with longer path delay seldom activate. In addition, the data distribution of deep learning applications leads those paths to activate rarely. According to this characteristic, we propose an Approximate Systolic Array Processor (ASAP), which combines both approximate computing and variable-latency design. With the technique which is similar to randomly drop partial connections within a deep neural network, we implement voltage under-scaling on our proposed DL accelerator to improve the power consumption of systolic arrays with negligible accuracy loss. In our experimental results of hand-written digit recognition and image classification applications, ASAP can obtain 47%~51% power saving over a baseline systolic array based on the architecture of Google’s TPU with 1% loss in classification accuracy.
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