使用多層感知器類神經網路之蒜頭選別機__臺灣博碩士論文知識加值系統

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本論文永久網址 :

研究生:

蔣序承

研究生(外文):

CHIANG, HSU-CHENG

論文名稱:

使用多層感知器類神經網路之蒜頭選別機

論文名稱(外文):

A Garlic Sorting Machine Using Multi-layer Perceptron Neural Network

指導教授:

陳銘志

指導教授(外文):

CHEN, MING-CHIH

口試委員:

徐偉智、吳毓恩、陳銘志、陳建興

口試委員(外文):

HSU, WEI-CHIH 、 WU, YU-EN 、 CHEN, MING-CHIH 、 CHEN, CHIEN-HSING

口試日期:

2018-07-11

學位類別:

碩士

校院名稱:

國立高雄第一科技大學

系所名稱:

電子工程系碩士班

學門:

工程學門

學類:

電資工程學類

論文種類:

學術論文

論文出版年:

2018

畢業學年度:

105

語文別:

中文

論文頁數:

56

中文關鍵詞:

類神經網路、蒜頭辨識、影像處理、硬體加速

外文關鍵詞:

Neural Network 、 Garlic Sorting 、 Image Processing 、 Hardware Acceleration

相關次數:

被引用: 1
點閱:452
評分:
下載:110
書目收藏:1

本論文開發一套可裝設在蒜頭選別機上的影像辨識系統，透過電腦視覺檢察蒜頭外表是否損壞，讓農民在分類蒜頭時能更精準快速且減少人力。本論文使用了軟體與硬體設計技術來開發以多層感知器類神經網路之蒜頭選別機。首先使用個人電腦搭配OpenCV提供的多層感知器類神經網路(Multi-Layer Perceptron Neural Network, MLP-NN)訓練套件，搭配自行拍攝的樣本圖片，透過統計的方法來產生灰階共現矩陣(Gray-Level Co-Occurrence Matrix, GLCM)，再由此GLCM計算出特徵值如：entropy、contrast，並輸入至MLP-NN函式內訓練，最後再將訓練後的權重輸入至FPGA內，即可達到實時的影像辨識系統。
為了達到低延遲與高速運算的功能，硬體部分採用的是Digilent Nexys 4 DDR FPGA開發版，將MLP-NN的主要結構與計算方法實作在板子上的XC7A100T-1CSG324C晶片上，使用定點數格式達到了只需2510個Flip-Flop(FF)、6054個Look-Up Table(LUT)、208個DSP48E元件，即可達到93.87%的準確度。

The thesis develops an image recognition system that can be installed on the garlic sorting machine to check whether the garlic is damaged. The farmer can process the garlic more accurately and quickly. The garlic machine can reduce the manpower while classifying the garlic. The system utilizes software and hardware design techniques to develop a garlic sorter with a multi-layer perceptron neural network. Firstly, the system uses a personal computer to perform a Multi-Layer Perceptron Neural Network (MLP-NN) training kit written by OpenCV software. The training kit uses self-photographed sample images to generate Gray-Level Co-Occurrence Matrix (GLCM) by a statistical method. Then the GLCM calculates the characteristic values such as entropy and contrast. These values are inputted into the MLP-NN function for training. After that, the weight values generated from training are realized to a Field Programming Gate Array (FPGA) chip. The MLP-NN function is realized with FPGA chip for accelerating the garlic sorting process.
In order to achieve low-latency and high-speed system performance, the MLP-NN is realized by a XC7A100T-1CSG324C chip on Digilent Nexys 4 DDR FPGA development board. It uses only 2510 Flip Flops, 6054-bit Lookup Table, and 208 DSP48E of the FPGA chip. The system can achieve 93.87% accuracy with hardwired MLP-NN function.

中文摘要 I
英文摘要 II
致謝 III
目錄 IV
表目錄 VI
圖目錄 VII
一、緒論 1
1.1 動機與目的 1
1.2 研究工具介紹 2
二、文獻探討 4
2.1 影像辨識之方法 4
2.2 應用感測器或其他技術 6
三、系統架構與實作方法 7
3.1. 系統架構 7
3.1.1. 系統介紹 7
3.1.2. 訓練階段 (Training Phase) 9
3.1.3. 測試階段 (Testing Phase) 20
3.2 硬體平台設計 23
3.2.1 FPGA開發版 23
3.2.2 硬體架構 23
3.2.3 硬體資源 28
3.2.4 樹莓派讀取圖片與串列輸出 28
四、實驗結果 31
4.1 以內建之MLP PREDICT方法測試 31
4.2 以實際架構與權重進行測試 32
4.3 以FPGA模擬測試 34
4.4 實際燒錄至FPGA上測試 38
五、結論與未來展望 42
六、參考文獻 43

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